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1 www.semtech.com sc2602l synchronous voltage mode controller for distributed power supply power management applications revision: january 05, 2006 typical application circuit ? r ds(on) current sensing ? output voltage can be programmed as low as 0.8v ? on-chip power good and ovp functions ? small size with minimum external components ? soft start ? enable function ? so-14 package is fully weee and rohs compliant ? microprocessor core supply ? low cost synchronous applications ? voltage regulator modules (vrm) ? ddr termination supplies ? networking power supplies ? sequenced power supplies the sc2602l is low-cost, full featured, synchronous volt- age-mode controller designed for use in single ended power supply applications where efficiency is of primary concern. synchronous operation allows for the elimina- tion of heat sinks in many applications. the sc2602l is ideal for implementing dc/dc converters needed to power advanced microprocessors in low cost systems, or in distributed power applications where efficiency is important. internal level-shift, high-side drive circuitry, and preset shoot-through control, allows the use of inexpen- sive n-channel power mosfets. sc2602l features include temperature compensated voltage reference, triangle wave oscillator and current sense comparator circuitry. power good signaling, shut- down, and over voltage protection are also provided. the sc2602l operates at a fixed 200khz which is for optimum compromise between efficiency, external com- ponent size, and cost. two sc2602l can be used together to sequence two voltage regulators for power up in telecom systems. the power good of the first sc2602l connected to the en- able of the second sc2602l makes this possible. figure 1. typical distributed power supply ? synchronous operation for high efficiency (95%) features r2 r7 r3 c3 + c2 q2 q1 l1 c6 ss/shdn r6 c10 + c9 r8 5v in 12v in r1 c1 c8 r4 pwrgd v_pullup ovp 2.5v out gnd gnd c5 u1 sc2602l vcc 1 pwrgd 2 ovp 3 ocset 4 phase 5 dh 6 pgnd 7 dl 8 bstl 9 bsth 10 comp 12 ss/shdn 13 gnd 14 sense 11 r5 c7 c4 d1 description
2 ? 2005 semtech corp. www.semtech.com power management sc2602l electrical characteristics absolute maximum ratings r e t e m a r a pl o b m y sm u m i x a ms t i n u d n g o t l t s b , c c vv n i ) e g r u s v 0 2 ( 6 1 o t 0 . 1 -v d n g o t d n g p 5 . 0 v d n g o t e s a h p ) 1 ( ) e g r u s v 0 2 ( 8 1 o t 5 . 0 -v e s a h p o t h t s b ) e g r u s v 0 2 ( 6 1v e s a c o t n o i t c n u j e c n a t s i s e r l a m r e h t c j 5 4w / c t n e i b m a o t n o i t c n u j e c n a t s i s e r l a m r e h t a j 5 1 1w / c e g n a r e r u t a r e p m e t g n i t a r e p ot a 5 8 + o t 0 4 -c e r u t a r e p m e t n o i t c n u j m u m i x a mt j 5 2 1c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 6 -c . c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt d a e l 0 0 3c ) l e d o m y d o b n a m u h ( g n i t a r d s ed s e2v k unless specified: v cc = 4.75v to 12.6v; gnd = pgnd = 0v; v bstl = 12v; v bsth-phase = 12v; t j = 25 o c r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u y l p p u s r e w o p e g a t l o v y l p p u sv c c 2 . 46 . 2 1v t n e r r u c y l p p u sv = n e c c 60 1a m n o i t a l u g e r e n i lv o v 5 . 2 =5 . 0% r e i f i l p m a r o r r e e c n a t c u d n o c s n a r tg m 8 . 1s m ) l o a ( n i a g 0 5b d s a i b t u p n i 58 a r o t a l l i c s o y c n e u q e r f r o t a l l i c s o 0 0 2z h k e l c y c y t u d x a m r o t a l l i c s o0 95 9% k a e p o t k a e p p m a r l a n r e t n i 1v s r e v i r d t e f s o m k n i s / e c r u o s h d, v 5 . 4 = h d - h t s b v 2 = e s a h p - h d 1a k n i s / e c r u o s l d. v 5 . 4 = l d - l t s b v 2 = . d n g p - l d 1a note: (1) -1.5v to 20v for 25ns repetitive every cycle. exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied. exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.
3 ? 2005 semtech corp. www.semtech.com power management sc2602l electrical characteristics (cont.) (1) specification refers to application circuit (figure 1). unless specified: v cc = 4.75v to 12.6v; gnd = pgnd = 0v; v bstl = 12v; v bsth-phase = 12v; t j = 25 o c note: r e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u n o i t c e t o r p e g a t l o v d l o h s e r h t p v o 0 2% t n e r r u c e c r u o s p v ov p v o v 3 =0 1a m d l o h s e r h t d o o g r e w o p8 82 1 1% e m i t d a e d5 40 0 1s n ) k n i s i ( t e s t n e r r u c r e v ov 0 . 2 4 ? 2005 semtech corp. www.semtech.com power management sc2602l pin configuration ordering information pin descriptions e c i v e d ) 2 ( y c n e u q e r fe g a k c a p ) 1 ( t r t s l 2 0 6 2 c sz h k 0 0 24 1 - o s b v e l 2 0 6 2 c sd r a o b n o i t a u l a v e notes: notes: notes: notes: notes: (1) only available in tape and reel packaging. a reel contains 2500 devices. (2) lead free product. this product is fully weee and rohs compliant. (14-pin soic) top view note: note: note: note: note: (1) all logic level inputs and outputs are open collector ttl compatible. gnd comp sense bsth bstl dl ss / shdn vcc ovp ocset phase dh pgnd pwrgd # n i pe m a n n i pn o i t c n u f n i p 1c c v. e g a t l o v y l p p u s p i h c 2d g r w p . e g a t l o v t u p u o t c e r r o c s e t a c i d n i h g i h c i g o l . t u p t u o r o t c e l l o c n e p o 3p v o v * 2 . 1 > e s n e s v n e h w a m 0 1 t s a e l t a e c r u o s . t u p t u o n o i t c e t o r p e g a t l o v r e v o . g b 4t e s c o. t n i o p p i r t t n e r r u c r e v o r e t r e v n o c e h t t e s 5e s a h p. s t e f s o m e h t n e e w t e b e d o n e s a h p e h t m o r f t u p n i 6h d. t u p t u o r e v i r d e d i s h g i h 7d n g p. d n u o r g r e w o p 8l d. t u p t u o r e v i r d e d i s w o l 9l t s b. r e v i r d e d i s w o l , p a r t s t o o b 0 1h t s b. r e v i r d e d i s h g i h , p a r t s t o o b 1 1e s n e s. t u p n i e s n e s e g a t l o v 2 1p m o c. n i p n o i t a s n e p m o c 3 1n d h s / s s . t e f m o t t o b f o e c r u o s o t t c e n n o c . r o t a l u g e r h c m g v 5 . 1 e h t r o f d n u o r g n r u t e r e v i r d e t a g 4 1d n g. d n u o r g l a n g i s
5 ? 2005 semtech corp. www.semtech.com power management sc2602l block diagram synchronous buck converter the output rail is regulated by a synchronous, voltage- mode pulse width modulated (pwm) controller. this section has all the features required to build a high effi- ciency synchronous buck converter, including ?power good? flag, shut-down, and cycle-by-cycle current limit. the output voltage of the synchronous converter is set and controlled by the output of the error amplifier. the external resistive divider reference voltage is derived from an internal trimmed-bandgap voltage reference (see fig. 1). the inverting input of the error amplifier receives its voltage from the sense pin. the internal oscillator uses an on-chip capacitor and trimmed precision current sources to set the oscillation frequency to 200khz. the triangular output of the oscil- lator sets the reference voltage at the inverting input of the comparator. the non-inverting input of the compara- tor receives it?s input voltage from the error amplifier. when the oscillator output voltage drops below the er- ror amplifier output voltage, the comparator output goes high. this pulls dl low, turning off the low-side fet, and dh is pulled high, turning on the high-side fet (once the cross-current control allows it). when the oscillator voltage rises back above the error amplifier output volt- age, the comparator output goes low. this pulls dh low, turning off the high-side fet, and dl is pulled high, turn- ing on the low-side fet (once the cross-current control allows it). as sense increases, the output voltage of the error amplifier decreases. this causes a reduction in the on- time of the high-side mosfet connected to dh, hence lowering the output voltage. under voltage lockout the under voltage lockout circuit of the sc2602l as- sures that the high-side mosfet driver outputs remain in the off state whenever the supply voltage drops below set parameters. lockout occurs if v cc falls below 4.1v. normal operation resumes once v cc rises above 4.2v. over-voltage protection the over-voltage protection pin (ovp) is high only when the voltage at sense is 20% higher than the target value programmed by the external resistor divider. the ovp pin is internally connected to a pnp?s collector. power good the power good function is to confirm that the regulator outputs are within +/-10% of the programmed level. pwrgd remains high as long as this condition is met. pwrgd is connected to an internal open collector npn transistor. theory of operation +10% -10% 0.8v +20% drvh drvh cross current control drvl drvl s r qb s r qb under voltage over current oscillator one shot pwm fault error amp vbg vbg vcc vcc 200ua 10ua 1.5ua 0.6v 0.8v vcc pwrgd ovp comp sense ss/shdn pgnd ocset bsth phase bstl dl dh gnd
6 ? 2005 semtech corp. www.semtech.com power management sc2602l soft start initially, ss/shdn sources 10a of current to charge an external capacitor. the outputs of the error amplifiers are clamped to a voltage proportional to the voltage on ss/shdn. this limits the on-time of the high-side mosfets, thus leading to a controlled ramp-up of the output voltages. r ds(on) current limiting the current limit threshold is set by connecting an ex- ternal resistor from the v cc supply to ocset. the volt- age drop across this resistor is due to the 200a inter- nal sink sets the voltage at the pin. this voltage is com- pared to the voltage at the phase node. this compari- son is made only when the high-side drive is high to avoid false current limit triggering due to uncontributing measurements from the mosfets off-voltage. when the voltage at phase is less than the voltage at ocset, an overcurrent condition occurs and the soft start cycle is initiated. the synchronous switch turns off and ss/ shdn starts to sink 1.5a. when ss/shdn reaches 0.8v, it then starts to source 10a and a new cycle be- gins. hiccup mode during power up, the ss/shdn pin is internally pulled low until vcc reaches the undervoltage lockout level of 4.2v. once v cc has reached 4.2v, the ss/shdn pin is released and begins to source 10a of current to the external soft-start capacitor. as the soft-start voltage rises, the output of the internal error amplifier is clamped to this voltage. when the error signal reaches the level of the internal triangular oscillator, which swings from 1v to 2v at a fixed frequency of 200khz, switching oc- curs. as the error signal crosses over the oscillator sig- nal, the duty cycle of the pwm signal continues to in- crease until the output comes into regulation. if an over- current condition has not occurred the soft-start voltage will continue to rise and level off at about 2.2v. applications information (cont.) an over-current condition occurs when the high-side drive is turned on, but the phase node does not reach the voltage level set at the ocset pin. the phase node is sampled only once per cycle during the valley of the tri- angular oscillator. once an over-current occurs, the high- side drive is turned off and the low-side drive turns on and the ss/shdn pin begins to sink 1.5a. the soft- start voltage will begin to decrease as the 1.5a of cur- rent discharges the external capacitor. when the soft- start voltage reaches 0.8v, the ss/shdn pin will begin to source 10a and begin to charge the external capaci- tor causing the soft-start voltage to rise again. again, when the soft-start voltage reaches the level of the in- ternal oscillator, switching will occur. if the over-current condition is no longer present, nor- mal operation will continue. if the over-current condition is still present, the ss/shdn pin will again begin to sink 1.5a. this cycle will continue indefinitely until the over- current condition is removed. in conclusion, below is shown a typical ?12v application circuit? which has a bsth voltage derived by bootstrapping input voltage to the phase node through diode d1. this circuit is very useful in cases where only input power of 12v is available. in order to prevent substrate glitching, a small-signal di- ode should be placed in close proximity to the chip with cathode connected to phase and anode connected to pgnd.
7 ? 2005 semtech corp. www.semtech.com power management sc2602l application circuit typical 12v application circuit with bootstrapped bsth r3 10 r7 r1 5k c4 10u q2 q1 l1 4uh + c3 820u/16v + c10 1200u/6.3v c7 1.0u ss/shdn r6 c2 1.0u c11 10u 12v in r8 2.2 c6 0.1u r2 1.74k c1 0.1u c8 1.0u r4 1k pwrgd +5v ovp 3.3v out gnd gnd d1 1n1418 u1 sc2602l vcc 1 pwrgd 2 ovp 3 ocset 4 phase 5 dh 6 pgnd 7 dl 8 bstl 9 bsth 10 comp 12 ss/shdn 13 gnd 14 sense 11 r5 9.6k c9 36n c5 0.1u d2 1n4148
8 ? 2005 semtech corp. www.semtech.com power management sc2602l pin descriptions typical characteristics output ripple voltage ch1: vo_rpl 1. v in = 5v; v o = 3.3v; i out = 12a gate drive waveforms ch1: top fet ch2: bottom fet ch1: vo_rpl 2. v in = 5v; v out = 1.3v; i out = 12a ch1: top fet ch2: bottom fet
9 ? 2005 semtech corp. www.semtech.com power management sc2602l ch1: vo_rpl 2. v in = 5v; v out = 1.3v; i out = 12a ch1: top fet ch2: bottom fet typical characteristics (cont.)
10 ? 2005 semtech corp. www.semtech.com power management sc2602l typical characteristics (cont.) hiccup mode ch1: vin ch2: vss ch3: top gate ch4: vout vin = 5v vout = 3.3v vbst = 12v iout = s.c. iout = s.c. iout = s.c. iout = s.c. iout = s.c. ch1: vin ch2: vss ch3: top gate ch4: vout vin = 5v vout = 3.3v iout = 2a vbst = 12v start up mode
11 ? 2005 semtech corp. www.semtech.com power management sc2602l the control model of sc2602l control loop small signal can be depicted in fig. 2. this model can also be used in spice kind of simulator to generate loop gain bode plots. the bandgap reference is 0.8v and trimmed to +/-1% accuracy. the desired output voltage can be achieved by setting the resistive divider network, r1 and r2. the error amplifier is transconductance type with fixed gain of: the compensation network includes a resistor and a capacitor in series, which terminates from the output of the error amplifier to the ground. this device uses voltage mode control with input volt- age feed forward. the peak-to-peak ramp voltage is proportional to the input voltage, which results in an ex- cellent performance to reject input voltage variation. the pwm gain is inversion of the ramp amplitude, and this gain is given by: where the ramp amplitude (peak-to-peak) is 1.0 volts when input voltage is 12 volts. the total control loop-gain can then be derived as follows: ts () t o 1sr . c . sr . c . . 1sr c . c o . 1sr c c o . l r o . s 2 l . c o . 1 r c r o . . g pwm 1 v ramp t o g m g pwm ? v in ? r ? v bg v o ? ? ? ? ? ? := the task here is to properly choose the compensation network for a nicely shaped loop-gain bode plot. the following design procedures are recommended to ac- complish the goal: (1) calculate the corner frequency of the output filter: (2) calculate the esr zero frequency of the output filter capacitor: (3) check that the esr zero frequency is not too high. if this condition is not met, the compensation structure may not provide loop stability. the solution is to add some electrolytic capacitors to the output capacitor bank to correct the output filter corner frequency and the esr zero frequency. in some cases, the filter inductance may also need to be adjusted to shift the filter corner frequency. it is not recommended to use only high fre- quency multi-layer ceramic capacitors for output filter. f esr f sw 5 < f o 1 2 ? lc o ? ? := f esr 1 2 ? r c ? c o ? := (4) choose the loop gain cross over frequency (0 db frequency). it is recommended that the crossover fre- quency is always less than one fifth of the switching frequency : if the transient specification is not stringent, it is better to choose a crossover frequency that is less than one tenth of the switching frequency for good noise immunity. the resistor in the compensation network can then be cal- culated as: when f x_over f sw 5 r 1 g pwm v in ? g m ? f esr f o ? ? ? ? ? 2 ? f x_over f esr ? ? ? ? ? ? v o v bg ? ? ? ? ? ? := f o f esr < f x _over < fig. 2. sc2602l small signal model. g m 1.8 ma . v c vbg 1.25vdc l rc r co gpwm ea ro r2 vin r1 0.5vdc 0.8vdc
12 ? 2005 semtech corp. www.semtech.com power management sc2602l or r 1 g pwm v in ? g m ? f o f esr ? ? ? ? ? 2 ? f x_over f o ? ? ? ? ? ? v o v bg ? ? ? ? ? ? := when (5) the compensation capacitor is determined by choos- ing the compensator zero to be about one fifth of the output filter corner frequency: (6) the final step is to generate the bode plot, either by using the simulation model in fig. 2 or using the equa- tions provided here with mathcad. the phase margin can then be checked using the bode plot. usually, this design procedure ensures a healthy phase margin. (7) an additional capacitor should be reserved at the compensation pin to ground to have another high fre- quency pole. an example is given below to demonstrate the proce- dure introduced above. the parameters of the power supply are given as : f esr f o < f x _over < f zero f o 5 c 1 2 . r . f zero . the parameters of the power supply are given as : step 1. output filter corner frequency step 2. esr zero frequency: step 3. check the following condition: f esr f sw 5 < which is satisfied in this case. step 4. choose crossover frequency and calculate compensator r: r4.8k ? = step 5. calculate the compensator c: step 6. generate bode plot and check the phase mar- gin. in this case, the phase margin is about 85 o c that ensures the loop stability. applications information (cont.) v in 12 v . v o 3.3 v . i o 12 a . f sw 200 k hz . l4 h . c o 1200 f . r c 0.02 ? . v bg 0.8 v . v ramp 1v . g m 1.8 ma . v f o 2.516 k hz = f esr 7.958 k hz = f x_over 20 k hz = c 65.886 nf =
13 ? 2005 semtech corp. www.semtech.com power management sc2602l applications information (cont.) bode plot of the control loop 0.01 0.1 1 10 100 1 . 10 3 50 0 50 100 loop gain mag (db) mag i () f i khz 0.01 0.1 1 10 100 1 . 10 3 180 135 90 45 0 loop gain phase (degree) phase i () f i k hz
14 ? 2005 semtech corp. www.semtech.com power management sc2602l semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805)498-2111 fax (805)498-3804 contact information outline drawing - s0-14 land pattern - s0-14 see detail detail a a .050 bsc .236 bsc 14 .010 .150 .337 .154 .341 .012 - 14 0.25 1.27 bsc 6.00 bsc 3.90 8.65 - .157 .344 3.80 8.55 .020 0.31 4.00 8.75 0.51 bxn 2x n/2 tips seating aaa c e/2 2x 3 a d a1 e1 bbb c a-b d ccc c a2 (.041) .004 .008 - .028 - - - - 0 .016 .007 .049 .004 .053 8 0 0.20 0.10 - 8 0.40 0.17 1.25 0.10 .041 .010 .069 .065 .010 1.35 (1.04) 0.72 - 1.04 0.25 - - - 1.75 1.65 0.25 0.25 - .010 .020 0.50 - c l (l1) 01 0.25 gage plane h h plane n 12 a e d c h b 3. dimensions "e1" and "d" do not include mold flash, protrusions or gate burrs. -b- controlling dimensions are in millimeters (angles in degrees). datums and to be determined at datum plane n otes: 1. 2. -a- -h- side view r eference jedec std ms-012, variation ab. 4 . l1 ccc aaa bbb 01 n dim e1 d a1 a2 dimensions millimeters min e l h e b c inches nom min a max max nom e z g y p (c) x this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. n otes: 1. r eference ipc-sm-782a, rlp no. 302a. 2 . .291 .087 .024 .118 (.205) inches dimensions z p y x dim c g millimeters .050 (5.20) 7.40 2.20 0.60 3.00 1.27

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